The present invention relates to a semiconductor device, a method of manufacturing a semiconductor device, and a testing method of the semiconductor device, and in particular to a technology effectively applicable to multichip configurations in which a semiconductor chip such as a microcomputer and a semiconductor chip such as a dynamic RAM (Random Access Memory) are mounted in a single package, system-in-package structures, or what is obtained by stacking multiple semiconductor packages in multiple layers.
There has been a trend in advance in semiconductor technology to construct multiple semiconductor chips as a single semiconductor device in a package configuration to construct an electronic system such as a chip for microcomputer or a DRAM chip. When a combination of semiconductor chips closely related to each other, for example, a combination of a microcomputer chip and a dynamic RAM (DRAM) is selected, one system can be mounted in a package and a so-called SiP (System in Package) can be achieved. An example of a semiconductor device in multichip configuration is disclosed in Japanese Unexamined Patent Publication No. 2004-235352. Meanwhile, Japanese Unexamined Patent Publication No. 2006-038678 discloses the application of an on-board ICE (In-Circuit Emulator) module to a burn-in test system and a burn-in test method for chips for microcomputer.
As a semiconductor package in a configuration different from the above-mentioned SiP, there is package on package (PoP) disclosed in Japanese Unexamined Patent Publication No. 2007-123454. The SiP is constructed by mounting multiple chips over one wiring substrate. In contrast to this, the PoP is a system in a stacked package constructed, for example, as follows: a package comprised of a wiring substrate mounted with a microcomputer chip and a package comprised of a wiring substrate mounted with a memory chip are prepared; and these packages are stacked and the chips are coupled together.    [Patent Document 1]    Japanese Unexamined Patent Publication No. 2004-235352    [Patent Document 2]    Japanese Unexamined Patent Publication No. 2006-038678    [Patent Document 3]    Japanese Unexamined Patent Publication No. 2007-123454